News

Join Doulos at DVCon 2009. Tap in to our industry leading technical expertise at San Jose this year and learn from a Doulos expert in the following tutorials:


Doulos to present Cortex-M3™ KnowHow at Embedded World. Engineers attending the March 3-5 Embedded World event in Nurenberg, Germany can now find out how to get the best out of the ARM® Cortex-M3™ debug features direct from Doulos experts. This 3 hour intermediate level workshop explains features and interaction of various ARM Cortex-M3 debug components, explores the differences between ARM Cortex-M3, rev1 and rev2 and includes a demonstration of some of the key features, together with hints and tips on how to get the best out of the the Cortex-M3 debug features. More>>

Doulos contributes ARM content to embedded systems book. Doulos yet again demonstrates its ARM expertise as guest authors of the popular embedded systems book 'C und C++ für Embedded Systems,' contributing the first German language introduction to ARM Cortex-M3 Architecture. The book provides practical examples, one of which Doulos has delivered and is available for free download in the ARM KnowHow section of the website. More>>

New ARM® class added to Doulos RapidGain™ series of 1-day training events. The RapidGain™ series delivers a combination of experience and knowledge in key topic areas …all in a single day. At a fraction of the cost of standard, full-scope training classes, they represent exceptional value and make focussed training accessible even to the most budget conscious or time constrained engineers. This latest addition to the series is aimed at engineers interested in incorporating ARM Cortex-M3™ based microcontrollers (MCUs) into their designs. It enables new and prospective users to rapidly gain the hands-on experience and understanding they need to get started. RapidGain™ Designing with ARM Cortex-M3 Based Microcontrollers includes a valuable independent comparison of available MCU features, which will help engineers make the right choice for their projects. More >>

Doulos supports Altera's 40nm Productivity Workshops. Doulos is actively supporting a series of FREE seminars organised by Altera, to boost productivity and help you get the most out of Altera devices. The workshops introduce the new 40nm families and, with the help of experts from Doulos and Altera, show you how to:

  • reduce development times
  • reduce and manage power
  • reduce the verification cycle

For more information and to register click here>>

Doulos shares its SystemVerilog expertise in the latest Aldec webinar series. Focusing on today's popular verification topics, the Aldec Verification Methodology Series of webinars (AVMS) provides design engineers with in-depth emerging verification trends and technologies in an "engineer to engineer" format. Doulos is pleased to partner with Aldec by presenting the following webinar: 'Improved, flexible design using SystemVerilog'. More >>

Doulos launches OVM 2.0 Golden Reference Guide - out now! Just weeks after the official release of OVM 2.0, Doulos has published the brand new, and much anticipated, OVM Golden Reference Guide. Fully supporting OVM 2.0, this new addition to the popular GRG series, complements the OVM User Guide, and underlines Doulos' market leading credentials in the development and delivery of up-to-the-minute SystemVerilog Training. Read more and buy online >>

New SystemC TLM-2.0 training announced . The new 3-day 'SystemC Modeling using TLM-2.0' class gives delegates the unique opportunity to hear the features of TLM-2.0 explained by people who worked at the heart of the OSCI standard development. Authorative and comprehensive, it forms the third step of the Doulos 3-step learning Path for effective SystemC use. More >>

Professional FPGA Designer Programme addresses critical design needs.
European Engineers tackling designs using Altera or Xilinx devices and tools now have a much needed answer to their design problems. Altera Professional Designer™ and Xilinx Professional Designer™ programmes provide the best combination of HDL, design flow and techncial training modules. Engineers and their managers can now optimise time invested in training and achieve ellusive design performance goals. Find out more about individual classes here >>


Page last updated 06 January 2009.