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RapidGain™ VHDL
Using Lattice

Duration - 1 day


View dates and locations
 Auf Deutsch

RapidGain™ VHDL Using Lattice is unique in offering delegates experience of the whole FPGA design flow, from VHDL coding and simulation through to downloading a design to a real device, all in a single day. Tightly focused and practical, this one-day hands-on training event will show new and prospective users how to get started wth VHDL and Lattice FPGAs.

Delegates will rapidly gain an understanding of the tools and processes involved in creating an FPGA design, achieving significant initial productivity gains. You will:

  • Understand the basic structure of Lattice FPGAs
  • Learn how VHDL is used to capture and simulate your FPGA design
  • See how the Lattice ispLever software implements your design, step by step
  • Program the FPGA on a development board

RapidGain™ VHDL Using Lattice is not available for in-house delivery.

Who should attend?

  • Digital designers thinking about making the first moves to VHDL and FPGA design
  • Managers who want to understand more about the process of creating FPGA designs and VHDL
  • Analogue or Systems designers who work with digital design teams

Prerequisites

No prior experience of VHDL or Lattice FPGAs and software is needed. You should have a basic understanding of digital logic design, and be computer-literate.

Structure and content

Getting Started with VHDL

What is an FPGA? • What is VHDL? • Tools for FPGA design • How does VHDL affect my design style? • Design flow • Design entity • Ports • Signals • STD_LOGIC • Signal assignment • Processes • Hierarchy • Testbenches • Simulation with Active HDL
LAB: Simulating a binary counter, using Active HDL

Using the ispLever Software

IspLever software • Creating a project • Specifying pin assignment constraints • Setting up timing constraints and generating timing reports using the Timing Analyzer • Implementing a design using the ispLever software • Gate-level simulation
LAB: Implementing counter using IspLever and programming a development board

Writing VHDL for Synthesis

Summary of VHDL constructs and their synthesis • Creating finite state machines Synchronous and Asynchronous controls • The NUMERIC_STD package
LAB Modifying the counter, re-implement and re-program the FPGA

Where do I go from here?

Summary and conclusions • Doulos VHDL, and FPGA training roadmap

Course Dates:
December 9th, 2008 Hannover, DE Enquire
January 20th, 2009 Munich, DE Enquire

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