Altera Designing with
Quartus II

Standard Level - 3 days

Auf Deutsch

Altera Designing with Quartus II is a 3-day course aimed at engineers designing Altera® FPGAs, including the Cyclone® and Stratix® families. You will learn how to make best use of the latest features of the Quartus® II software, including all the productivity and efficiency benefits of using TimeQuest Timing Analysis, Incremental Design and PowerPlay power analysis and optimisation.

Approximately 50% of class time is spent on practical exercises to reinforce the lectures. The exercises make use of a development board to emphasise the real-world application of the techniques learned.

Altera Designing with Quartus II is developed and maintained for Doulos by specialist partner ALSE based on source material from Altera. Doulos and ALSE are Approved Altera Training Partners.

Who should attend?

Existing users, who wish to become more productive by extending their knowledge of Quartus II and exploiting the latest features and techniques.

Design engineers who are new to Quartus II, and want quickly to get fully up to speed with all the key features of Quartus II. Please see the pre-requisites below.

What will you learn?

How to make best use of the full capability of the Quartus II software to implement your design.
How to specify timing constraints and perform static timing analysis using TimeQuest.
Use Incremental Compilation techniques, including creating LogicLock™ regions (Floorplanning) and Partitions to reduce compile times and more easily achieve timing closure.
Estimating, analysing and optimising power consumption.
Improve productivity and quality by automating the design flow using scripts.
Functional and timing simulation using ModelSim®.
Debugging designs using SignalTap® II and SignalProbe.

Pre-requisites

All participants must be computer literate and have a basic understanding of digital design.

The main course focus is on the more advanced features of Quartus II. A basic working knowledge of Quartus II would be beneficial, but is not absolutely essential. You can obtain this from the online tutorial included with Quartus II. This is also available online at www.altera.com.

Course Content

Quartus® II and the Design Flow

Review of Quartus II basics • Creating assignments and constraints • Dynamic checking • The Pin Planner • CSV import/export • Virtual pins • Creating and comparing revisions • Running Place and Route • Third party tool integration • Downloading and programming the target device • JTAG chains • Using non-Altera devices • Converting programming files and indirect JTAG programming (JIC)

Advanced Use of Quartus® II

Version-compatible databases • Optimisation options • WYSIWYG re-synthesis • Physical synthesis • Design analysis • Using the RTL, technology and state machine viewers • Cross-probing • Intelligent message suppression • Design rule checker (design rule assistant)

Understanding and Mastering TimeQuest and SDC Constraints

The TimeQuest Static Timing Analyser • Concepts • Interface • Presentation of Synopsys Design Constraints (SDC) format • SDC terminology • Using TimeQuest from the GUI and from SDC files • Understanding the TimeQuest reports • Practical applications to usual applications (constraining a single clock, input and output maximum and minimum delays, I/Os anlysis, PLLs, etc.) • Early timing estimation

Incremental Compilation

Preparing a project for incremental flow • Creating design partitions • Combining with floorplan constraints using LogicLock • Exporting and importing a design • Performance preservation • top-down and bottom-up flows

Power Analysis and Optimisation

Using PowerPlay • Early estimation and finer vector-based statistical estimation • Using the power optimisatin adviser

Design Flow Automation

For improved productivity and quality, design tasks and project management can be automated and secured with command-line and Tcl scripts: Project creation • File management, archiving, cleanup, compilation, result testing, etc.

Simulation

Functional simulation and post-layout timing simulation with ModelSim • Quick overview of ModelSim AE (Altera Edition) • RTL simulation, compilation and simulation scripts • Adapting the test bench to the timing model • Generation and compilation of the VITAL model & SDF file

SignalTap® II and SignalProbe

Take advantage of free Embedded Logic Analysers to debug your design. The three modes • Configuration • Using the Logic Anaylsis Interface • Capturing/displaying • Saving data • Taking advantage of the segmented mode • Using the MegaWizard • Advanced Triggering • Signal Probe and the logic analyser interface • Purpose and use

Design Space Explorer

Concepts and Use

In-System Memory Contents Editor

Concept and Use • Applications •

Additional Options for In-house Delivery

Designing with Quartus II is available both as a publicly scheduled course and for in-house delivery. On scheduled courses, all the topics listed above will be taught. Additional exercises and optional topics may be taught at the course leader's discretion, depending on the time available and on the interests of the delegates.

For in-house delivery, there is more scope for customising the course contents. In particular, the following modules are available. Please call Doulos to discuss your requirements.

Techniques for Optimising Area and Timing

Making your RTL code mor efficient • Optimising arithmetic •Resource sharing • Identifying and understanding the critical paths • Using the optimisation advisor • Physical synthesis and advanced options • Tips for improving RTL coding.

Advanced Timing Analysis with TimeQuest

Advanced concepts • Recovery/removal analysis • Optimising arithmetic • Resource sharing • Identifying and understanding the critical paths • Using the optimisation advisor • Physical synthesis and advanced options • Tips for imporving RTL coding.

SignalTap II

Advanced Triggering

Interfacing to External Memory

This module covers the use of Altera's memory interface IP, using the example of DDR memory: Customising and using a High Performance DDR memory controller in a Quartus II project • Verification using simulation, static timing analysis and in-system testing with SignalTap II • Understanding termination

Course Dates:
February 4th, 2009	Bournemouth, UK	Enquire
February 17th, 2009	Hannover, DE	Enquire
March 2nd, 2009	Eindhoven, NL	Enquire