Xilinx - DSP Design Using System Generator

Intermediate Level - 2 days

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The DSP Design Using System Generator course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

This course uses materials developed by Xilinx for delivery by Doulos, the authorised training partner for Xilinx in the UK and Ireland.

Who should attend?

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using MathWorks MATLAB and Simulink and want to use Xilinx System Generator for DSP design.

Pre-requisites

Experience with MATLAB and Simulink
Basic understanding of sampling theory

Software Tools

ISE™ 9.1i
SP2 with IP update 1
Xilinx System Generator 9.1
MathWorks MATLAB with Simulink R2006b

Skills gained

After completing this training, you will have the necessary skills to:

Describe the System Generator design flow for implementing DSP functions
Make best use of the FPGA capabilities and implement a design from algorithm concept to hardware simulation
Understand what low and high level functional blocks are available in System Generator
Recognise that hardware may be required for high-level abstraction
Identify the high-level blocks available for filter design
Perform hardware-in-the-loop simulation
Design a multiple clock-based System Generator system
Employ various design techniques for improving system performance

Course Outline

Please note: Target architecture includes Virtex™-4, VirtexII Pro and Spartan™-3E FPGAs

Day 1

Introduction to System Generator
Simulink Basics
Lab 1: Using Simulink
Basic Xilinx Design Capture
Lab 2: Getting Started with Xilinx System Generator
Signal Routing
Lab 3: Signal Routing
Implementing System Control
Lab 4: Implementing System Control

Day 2

Multi-Rate Systems
Lab 5: Designing a MAC-based FIR
Filter Design
Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block
Memories
Lab 7: Designing with Shared Memories
Achieving Higher Performance
Lab 8: Improving Design Performance

Lab Descriptions

Lab 1: Using Simulink
Learn how to use Simulink toolbox blocks and design a system.
Understand the effect of sampling rate.
Lab 2: Getting Started with Xilinx System Generator
Design a DSP48-based (ML403) or Multiply and Accumulator block-based (SP3E) 12 x 8 MAC.
Perform hardware-in-the-loop verification targeting an ML403 and/or Spartan™-3E FPGA starter board.
Lab 3: Signal Routing
Design padding and un-padding logic using signal routing blocks.
Lab 4: Implementing System Control
Design an address generator circuit using blocks and Mcode.
Lab 5: Designing a MAC-based FIR
Using a bottom-up approach, design a MAC-based band-pass FIR filter and verify through hardware-in-the-loop simulation using an ML403 and/or Spartan-3E FPGA starter board.
Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block
Design a band-pass FIR filter using the FIR Compiler block (ML403) or DAFIR block (SP3E) to demonstrate increased productivity.
Verify the design through hardware-in-the-loop using an ML403 and/or Spartan-3E FPGA starter board.
Lab 7: Designing with Shared Memories
Learn to use multiple System Generator blocks to design and implement a multi-clock domain system.
Verify the design in hardware using an ML403 and/or Spartan-3E FPGA starter board.
Lab 8: Improving Design Performance
Use the Timing Analyser block and other techniques to improve system performance.

Course Dates:
April 27th, 2009	Bournemouth, UK	Enquire