Comprehensive e

Standard Level - 5 days

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 Auf Deutsch

Comprehensive e is a 5-day training course providing one-stop project preparation for engineers in the application of e for verification. Including advanced material on best practice techniques, the course provides all the know-how needed for engineers to apply, exploit and create verification environments confidently and effectively.

The course comprises 2 modules:

• e for Test Writers (days 1-2) provides a solid grounding in the e language and coverage driven verification methodology. It is carefully designed to suit the needs of verification engineers whose projects already make use of an e-based verification environment. Such engineers typically focus on the creation of new test scenarios and the collection and analysis of coverage data. The course combines tutorial presentations with a progressive series of practical workshops based on a relevant sample verification problem, so that skills learnt can be reinforced through immediate practical application.
  
  
• Building an e Verification Environment (days 3-5) builds on the first two days' foundation and shows engineers how to create verification components and large, re-usable test environments using the standard e Reuse Methodology (eRM™) and eVCs.

Because Doulos is an independent company, delegates can choose from a range of leading VHDL or Verilog® simulation tools for use alongside the Specman Elite tool during the workshops.

Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time.

Who should attend?

• Engineers who wish to become skilled in the practical use of e for verification of large programmable logic or ASIC designs
• Engineers who are about to embark on their first e verification project or evaluation
• Engineers who have already acquired some practical experience in the use of e, but wish to consolidate and extend their knowledge within a training environment

What will you learn?

e for Test Writers

• Coverage driven verification methodology: using the design of coverage as a starting point for verification planning
• Enough syntax and semantics of the e language to enable you to use and understand an existing verification environment
• How to use and extend the sequence (structured stimulus) generation facilities of your existing test environment
• How to use e's functional coverage features to audit and improve the quality of verification

Building an e Verification Environment

• How to write e verification components that conform to the eVC standard
• Techniques for providing a flexible infrastructure that can readily be deployed and configured by users
• Designing and managing sophisticated stimulus using the Sequence mechanism
• A good understanding of all the language constructs required to build and maintain a verification environment, including the temporal syntax

Pre-requisites

Delegates need some familiarity with digital hardware design, at least to the level covered in the Doulos course Essential Digital Design Techniques. Familiarity with VHDL, Verilog or a software programming language, such as that gained from attending the Doulos courses Comprehensive VHDL or Comprehensive Verilog, is strongly recommended.

Delegates attending only the module Building an e Verification Environment must already have a working knowledge of e and the Specman Elite tool. This module is suitable for delegates who have some experience of working with an existing e verification environment, or who have recently attended the e for Test Writers module.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world and has made them sought after resources in their own right. Course fees include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• e Golden Reference Guide
• Tool tour guides (to support the tools and technologies of your choice)

Structure and Content

e for Test Writers (days 1-2)

Concepts of Coverage-Driven Methodology

Contrasting testbench automation with a traditional HDL verification methodology • Benefits of using e in testbench automation • Designing an e test environment using coverage driven verification methodology

e Language Basics

Basics of object-oriented programming • Data types and structs • Comments and source files • Import • Enumerated types and subtypes • Writing numeric values and other constants

Stimulus Creation

Structs and fields • Generation and constraints • The constraint solver at work • Implication constraints • Pre-run generation • Methods and procedural code • Extension of methods • Test phases and getting methods to run • On-the-fly generation • Lists • Displaying information using the message system • Soft constraints and constraint resolution • Generation order considerations

Stimulus Variation

The need for flexible extension of stimulus data types • Introducing when inheritance • Control fields as a way to influence constraints • Extension of enumerated types • Applications of conditional inheritance to verification problems • Types and subtypes

Interacting with the Simulator

Predefined execution flow in Specman - the test phases • Accessing HDL signal values from Specman using ports • Threads of execution • Events to define clocks to synchronise with the DUT • Events to indicate that something has happened • Time-Consuming Methods (TCMs) to interact with the simulator • wait and sync • Introduction to the temporal syntax

Using Sequences

How a Bus Functional Model (BFM) is used within your testbench • Using eRM sequences that are provided in an existing test environment • Extending a predefined sequence library for use in your own test cases • The do action and body method • Configuring the MAIN sequence

Coverage Basics

The need for functional coverage • Coverage features in e • What does functional coverage tell us? • Using coverage data to audit the quality of tests • Coverage driven verification methodology: using coverage as the starting point for verification planning • Creating a coverage group • Specifying coverage items • Transition and cross coverage • Group and item options • Interpreting the coverage results

Building an e Verification Environment (days 3-5)

Architecting the Verification Environment

Techniques for creating re-usable verification IP • The eRM library and language extensions • Structure of a typical eVC • How eRM fits in to a typical test environment • Units and like inheritance • The static unit hierarchy • Elaboration-time phases • Method ports • Port binding • File organisation • Documentation and the eDoc tool • eRM as a template for constructing environments - agent and environment organisation • eRM resources

BFMs and Monitors

Implementing a BFM or monitor • Using ports to reach HDL signals • hdl_path • How the physical layer fits into eRM • Portability concerns • Placing ports in a signal map • Packing and unpacking

Sequence Environment

The environment developer's view of sequences • Three steps to creating a sequence • Applications of sequences • Running Specman in zero time • The scenario builder tool

Verification Environment API

Providing control over the environment topology • Active or passive? • More on soft constraints • Soft constraints as a hierarchy of range restrictions • Control fields to manage value-ranges • Constraints controlled by topology: eRM instance names

Data Checking

Methodology of checking • Checkers in the testbench architecture • Separating functionality from timing • Monitors facilitate checker re-use • Reference models • Creating and using a scoreboard • The check phase • Built-in deep compare and deep copy methods • Method ports as a means to connect checkers • dut_error and controlling check effects

Temporal Checking

The temporal syntax • expect and temporal-yield • Events in temporal expressions • Temporal operators • Some standard idioms

Advanced Specman Coverage

Understanding coverage collection in detail • Using the when option • Where to put coverage groups • Coverage extension • More on coverage options • Event, sequence and scenario coverage • Coverage to measure latency • Coverage on checkers • Re-use considerations

Controlling the Verification Environment

Handling warm reset during the simulation - the quit and rerun methods • Coordinating end-of-test using the objection mechanism • More on the message logger