Essential Verification Methodology

Foundation Level - 2 days

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 Auf Deutsch

Essential Verification Methodology is a comprehensive methodology course aiming to provide an overview of the functional verification process and the current range of technologies available to implement it successfully.

The course has no bias towards any particular design or verification language or EDA tools from any particular manufacturer. As such, it could be used as a precursor to a number of other Doulos verification-related courses, such as 'Assertion-Based Verification with PSL', 'Comprehensive e' or 'Modular SystemVerilog', each of which provides in-depth training and hands-on workshops in the corresponding language and methodology.

Pencil-and-paper exercises are included to reinforce and challenge the extent of learning, and comprise approx. 15% of class time.

Who should attend?

• Design engineers and verification engineers wishing to gain an overview and update their understanding of the various aspects of modern functional verification.
• Engineers with little or no experience in verification. This could include:
• Engineers from other disciplines (e.g. software design or digital hardware design) re-training for functional design verification involvement.
• Engineering managers requiring familiarisation with the verification process and up-to-date aspects of functional verification methodology.

What will you learn?

• A thorough understanding of the importance of functional verification, its definition, the motivation underlying its use and its terminology
• The preparation and maintenance of a verification plan
• Simulation and related technologies such as the development and use of design properties and assertions, testbench automation and transaction level modelling
• Formal verification methods - how to verify a design without test vectors, as well as the use of design properties
• Code coverage and functional coverage - how to measure progress in the verification process
• Hardware-assisted verification methods and technologies - ways to accelerate the verification process

Pre-requisites

Delegates require no prior involvement in verification, but should be familiar with the digital design process. Any knowledge of a hardware description language (HDL) or any other verification-associated languages, such as e or PSL, would be helpful but by no means essential.

Course materials

Doulos course materials are renowned for being the most comprehensive and user friendly available. Course fees include:

• Fully indexed course notes creating a complete reference manual
• Workbook of pencil-and-paper workshops to help you apply your knowledge

Structure & Content

Overview

Definitions, terminology • Functional verification flow and methods • Linting • Simulation • Debugging • Modelling • Coverage • Assertion-based verification • Formal methods

Verification Process

Verification Plan: creation and maintenance • Verification strategy • Test definition, generation and execution • Re-usable verification IP • Milestones and code reviews • Regression and stress testing • Verification metrics and bug-tracking

Testbenches

HDL testbenches • Testbench architecture • Bus Functional Models and data modelling • Testbench automation • Hardware Verification Languages (HVLs) • Object-oriented and aspect-oriented programming • Stimulus generation, directed, random and constrained-random • Response checking and self-checking testbenches • Variable latency, FIFOs and scoreboarding • Coverage-driven methodology and types of coverage

Properties and Assertions

Properties, their definition and use • Temporal properties • Assertions • Authoring of properties and assertions • Observability and functional coverage • Re-using properties

Formal Verification

Definitions, motivation and terminology • Equivalence checking • Property checking • Coverage • Safety, liveness, invariant • Assumptions • Dynamic formal verification

Hardware Prototyping

Hardware acceleration • Emulation and In-Circuit-Emulation (ICE) • FPGA Prototyping • Observability of internal design nodes • Synthesizable assertions

Appendix - Temporal Logic

Boolean algebra • Temporal logic: CTL and LTL • Fairness

Related courses

• Comprehensive SystemVerilog
• Comprehensive e
• Expert SystemC Verification
• Assertion-Based Verification with PSL
• Expert VHDL Design & Verification
• Expert Verilog Design & Verification