Expert VHDL Verification

Advanced Level - 3 days

view dates and locations
 Auf Deutsch

Expert VHDL Verification is an intensive advanced application class. It teaches engineers how to increase productivity by enhancing their VHDL coding and application skills. The syllabus focuses on test benches and ‘hot’ techniques for verification such as scoreboarding and Transaction Level Verification (TLV).

Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.

Expert VHDL Verification forms the last 3 days of the 5-day Doulos Expert VHDL class.

Who should attend?

Design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification

What will you learn?

• A set of VHDL language features that go beyond what is taught on a basic training class
• The principles and details of how to approach the problem of design verification using VHDL
• How to structure and write large and complex VHDL test benches
• The principles and details of how to write behavioural models of hardware components in VHDL
• A deeper understanding of the VHDL language and how to apply it, enabling you to troubleshoot VHDL simulation problems with ease
• An introduction to IEEE 1076-2007c (VHPI) and the proposed VHDL 2008

Pre-requisites

To maximise the training value, prior attendance of the Doulos Comprehensive VHDL (or equivalent) class is required.

Training materials

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:

• Fully indexed class notes creating a complete reference manual
• Workbook full of practical examples to help you apply your knowledge
• Doulos VHDL Golden Reference Guide for language, syntax, semantics and tips
• Tour guides (to support the tools and technologies of your choice)

Structure and Content

VHDL Language

Subprograms, parameters, assigning signals • User defined packages • User defined array types • Record types, selected names, aggregates, arrays of records • Types, subtypes and overloading, conversion functions • Qualified expressions • Generics, string generics, array generics • Configurations, binding and dependencies, generic and port maps

Verification Environments and Methodology

The Verification Plan • Structure of a simple test bench • Structure of a complex test bench • Procedural stimulus generation • Reactive test benches • File I/O; TEXTIO and 'C' • Measuring delays • Monitoring internal signals • Generating random numbers • Collecting diagnostic data • Scoreboards • Coping with latency and Out-of-Order completion • Control files • Adding a user interface to a test bench • Writing behavioural models • Generic and parameterised test benches • How to implement functional coverage • How to implement run-time parameterisation • A re-usable generic approach to creating verification environments • Example code to take away

How VHDL works

Signal assignments • Events and inertial delay • Deltas Drivers and resolution functions • Wait statements • NOW • Static elaboration, the network model • Dynamic elaboration, elaborating arrays and files in subprograms • VHDL Attributes

Component Modeling

How to structure a behavioural model • Representing state • Example - behavioural modeling of a serial thermometer chip • Giving visibility of internal state • Modeling external timing relationships • Checking timing constraints using signal attributes • 1164 strength strippers • Handling 'X' on the inputs • Modeling memories • Modeling analogue blocks • Bus-functional models • Processor models • Foreign bodies for including C models for interfacing to emulators

Course Dates:

Price on request

Back to top