Xilinx - Designing with
Multi-Gigabit Serial I/O

Intermediate Level - 2 days

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Learn how to employ RockettIO™ GTP serial transceivers in your Virtex™-5 LXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B encoding, channel bonding, clock correction, and comma detection. Additional highlighted topics include use of te Architecture Wizard and synthesis and implementation considerations. This course balances lecture modules and practical hands-on labs.

This class uses materials developed by Xilinx for delivery by Doulos, the Authorised Training Provider for Xilinx in the UK and Ireland.

Who should attend?

FPGA designers and logic designers

Pre-requisites

  • Basic FPGA design experience (equivalent to the Fundamentals of FPGA Design class)
  • VHDL or Verilog HDL experience (as could be obtained by attending the Doulos 'Comprehensive Verilog' or 'VHDL for FPGA Design')
  • Synthesis and simulation experience
  • Knowledge of high-speed serial I/O protocols and standards (SONET, Gigabit Ethernet, InfiniBand) is a plus

Software Tools

  • Xilinx ISE 9.1i
  • Mentor Graphics ModelSim PE 6.2

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe and utilize the ports and attributes of the RocketIO™ multi-gigabit transceiver (GTP) in the Virtex™-5 LT FPGA
  • Effectively use the following features of the GTP
    - Comma detection, CRC, clock correction, and channel bonding
    - 8B/10B encoding/decoding, programmable termination, and preemphasis
  • Use the GTP Wizared to instantiate GTP primitives in a design
  • Access appropriate reference material for board design issues
  • Power supply, oscillators, and trace design

Course Outline

Day 1
  • Introduction
  • Clocking and Resets
  • 8B/10B Disparity and Bypass
  • Lab 1 - 8B/10B Disparity and Bypass. Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
  • Commas and Data Alignment Details
  • Lab 2 - Commas and Data Alignment. Use programmable comma detection to align a serial data stream.
  • Cyclical Redundancy Check (CRC) Details
  • Lab 3 -CRC. Configure a CRC block using the CRC Wizard

Day 2
  • Clock Correction Details
  • Lab 4 - Clock Correction. Utilize the clock correction logic to compensate for frequency differences on the TX and RX side of a link.
  • Channel Bonding Details
  • Lab 5 - Channel Bonding. Modify a design to use two transceivers bonded together to form one virtual channel.
  • GTP Wizard Overview
  • Implementing a RocketIO Transciever Design
  • Lab 6 - Synthesis and Implementation. Use the GTP Wizard to configure RocketIO transceiver primitives. Instantiate the resulting component in a design, synthesize the design and implement the design.

Course Dates:
January 19th, 2009 Bournemouth, UK Enquire

Courses scheduled in s'Hertogenbosch are delivered by 'Arcobel', a Doulos Certified Training Provider (CTP) in the Benelux region.

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