Xilinx - Designing with PlanAhead

Intermediate Level - 2 days

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Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool from Xilinx. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design and I/O pin assignment.

Who should attend?

FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

Pre-requisites

Prior attendance of the Fundamentals and Design for Performance class, or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow.

Software Tools

  • Xilinx ISE Design Suite 10.1
  • PlanAhead 10.1

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • List the main features and benefits of the PlanAhead tool
  • Import designs into the PlanAhead tool project environment
  • Assign optimal I/O locations
  • Import HDL souces and elaborate and analyze an RTL netlist
  • Analyze design statistics, connectivity, timing and placement results
  • Run the Design Rule Checker (DRC)and Weighted Average Simultaneous Switching Output (WASSO) analysis
  • Partition and floorplan designs
  • Run ExploreAhead to try multiple implementation strategies
  • Import and analyze the implementation results to improve the floorplan
  • Floorplan to improve performance and consistency
  • Use block-based design and create reusable IP

Course Outline

Day 1
  • Course Overview
  • Lab 1 - Getting started with the PlanAhead tool. Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning.
  • I/O Pin Planning
  • Lab 2 - Assigning I/O Pins. Introductes the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
  • Design Analysis and Exploration
  • Lab 3 - Design and analysis exploration. Introduces the analysis features of the PlanAhead tool that enable early detection of potential design issues, alternate device selection, initial floorplanning direction, and post-implementation exploration.
  • Design partitioning and top-level floorplanning
  • Lab 4 - Design partitioning and top-level floorplanning. Introduces the concept of floorplanning. By using automated partitioning tools, you will create a top-level floorplan and experiment with sizing and shaping Pblocks based on resources assigned to them.
Day 2
  • Implementing a floorplanned design
  • Lab 5 - Implementation. Introduces the integration of the ISE software implementation tools with the PlanAhead tool. Also introduces the ExploreAhead tool for queuing multiple ISE software runs with varying strategies.
  • Floorplanning techniques
  • Lab 6 - Floorplanning. Describes how to analyze implementation results and to use that information to generate a floorplan aimed at increasing design performance.
  • Tuning a floorplan for performance
  • Lab 7 - Floorplan tuning. Introduces techniques to help close on timing
  • Block-based design and IP reuse
  • Lab 8 - Block-based design and IP reuse. Describes the steps to implement a block-based methodology that includes the creation and reuse of an IP module.
  • Floorplanning strategies
  • Course summary
Note - The labs provided within this course include the tutorials packaged with the PlanAhead tool.

Course Dates:
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